Automatic VHDL restructuring for RTL synthesis optimization and testability improvement

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transformation “VHDL restructuring”. A set of restructuring steps is presented aiming at partitioning any VHDL description while guaranteeing the semantic equivalence of the restructured description with the original one. The main motivation to restructuring is the identification and separation of the two parts (FSM+data-path) which can thus be analyzed by using “adhoc” synthesis, testability and design for testability algorithms. Promising results show that restructuring can sensibly impact on synthesis and testability.